SH7760 Datasheet, PDF (697/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
7
MDBS
0
R/W Master Data Buffer Select
This bit is used to select the data buffer. The data
buffer has the FIFO buffer mode and the single
buffer mode.
Clearing MDBS to 0 will select theFIFO buffer
mode. In the receive mode, while the RDF flag is
1 with the receive byte count in the FIFO buffer
reaches the byte count specified by RTRG3 to
RTRG0, SCL is held low. Reading the receive
data from the FIFO buffer will clear the RDF flag
to 0 and release SCL from low level.
Setting MDBS to 1 will select the single buffer
mode.
SCL will be held low from the moment the receive
data register receives a data packet until the MDR
flag is cleared to 0.
6
FSCL

5
FSDA

4
OBPC
0
3
MIE
0
R/W Force SCL
Controls the state of the I2C_SCL pin. Reading
this bit will return the value reflecting the current
state of I2C_SCL. When OBPC is 1, this bit
directly controls SCL on the bus.
Since this bit reflects the value on the I2C_SCL
pin directly, the read value (level) of this bit
(including the reset level) changes depending on
the I2C_SCL level.
R/W Force SDA
Controls the state of the I2C_SDA pin. Reading
this bit will return the value reflecting the busy
state on the I²C bus. When OBPC is 1, this bit
directly controls SDA on the bus.
The read value (level) of this bit (including the
reset level) reflects the busy state on the I²C bus.
0: The I²C bus is not busy
1: The I²C bus is busy
R/W Override Bus Pin Control
Setting OBPC to 1 will have FSDA and FSCL in
this register control the SDA and SCL lines
directly. This mode is used for testing purposes
only.
R/W Master Interface Enable
Setting MIE to 1 will enable the master interface.
Rev. 1.0, 02/03, page 647 of 1294