SH7760 Datasheet, PDF (1293/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

33.3.7 SCIF Module Signal Timing
Table 33.11 SCIF Module Signal Timing
(V_DDQ= 3.0 to 3.6V, V_DD= 1.5V, T_a= −40 to 85°C, C_L= 30pF, PLL2 on)
Module Item
SCIFn Input clock cycle (asynchronous)
Input clock cycle (synchronous)
Input clock pulse width
Input clock rise time
Input clock fall time
Transfer data delay time
Receive data setup time (synchronous)
Receive data hold time (synchronous)
Note: t_Pcyc : one Pck cycle time
Symbol Min. Max. Unit Figure Notes
t_Scyc
t_SCKW
t_SCKr
t
SCKf
t_TXD
t_RXS
t_RXH
4
—
t_Pcyc 33.52
10 — t_Pcyc 33.52
0.4 0.6 t_Scyc 33.52
— 0.8 t_Pcyc 33.52
— 0.8 t
33.52
Pcyc
—3
t_Pcyc 33.53
3
—
t_Pcyc 33.53
1
—
t_Pcyc 33.53
SCIFn_CLK
t_SCKW
t_Scyc
t_SCKf
t_SCKr
Figure 33.52 SCIFn_CLK Input Clock Timing
SCIFn_CLK
SCIFn_TXD
SCIFn_RXD
t_Scyc
t_TXD
t_TXD
t_RXS t_RXH
Figure 33.53 SCIF I/O Synchronous Mode Clock Timing
Rev. 1.0, 02/03, page 1243 of 1294