SH7760 Datasheet, PDF (183/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.6.3 ITLB Data Array 2
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H’F38 indicating ITLB data array 2 and the entry
is specified by bits [9:8].
In the data field, bit [3] indicates TC and bits [2:0] indicate SA.
The following two kinds of operation can be used on ITLB data array 2:
1. ITLB data array 2 read
SA and TC are read into the data field from the ITLB entry corresponding to the entry set in
the data field.
2. ITLB data array 2 write
SA and TC specified in the data field are written to the ITLB entry corresponding to the entry
set in the address field.
31
24 23
Address field _{1 1 1 1 0 0 1 1 1}
10 9 8 7
0
E
31
Data field
4320
TC
TC: Timing control bit SA[2:0]: Space attribute bits
E: Entry
: Reserved bits (write value should be 0, ^SA[2:0]
and read value is undefined )
Figure 6.14 Memory-Mapped ITLB Data Array 2
6.6.4 UTLB Address Array
The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, D, V, and ASID to be written to the address array are
specified in the data field.
Rev. 1.0, 02/03, page 133 of 1294