SH7760 Datasheet, PDF (1249/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

33.3.1 Clock and Control Signal Timing
Table 33.5 Clock and Control Signal Timing
(V_DDQ= 3.0 to 3.6V, V_DD= 1.5V, T_a= −40 to 85°C, C_L= 30pF, PLL2 on)
Item
Symbol Min. Max. Unit Figure
EXTAL clock PLL1 6-times/PLL2 operation f
EX
input
PLL1 12-times/PLL2 operation
frequency
PLL1/PLL2 not operating
16 34 MHz
16 22
1 34
DCK clock output
DCK clock output cycle time
DCK clock output low-level pulse width
DCK clock output high-level pulse width
DCK clock output rise time
DCK clock output fall time
DCK clock output low-level pulse width
DCK clock output high-level pulse width
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock
output
PLL1/PLL2 operation
PLL1/PLL2 not operating
f_OP2
t_DCcyc
t
DCOL1
t
DCOH1
t
DCOr
t_DCOf
t_DCOL2
t
DCOH2
t
EXcyc
t
EXL
t_EXH
t_EXr
t_EXf
f
OP
22 67 MHz
15 45 ns 33.4
1  ns 33.4
1  ns 33.4
 3 ns 33.4
 3 ns 33.4
3  ns 33.5
3  ns 33.5
30 1000 ns 33.1
3.5  ns 33.1
3.5  ns 33.1
 4 ns 33.1
 4 ns 33.1
25 67 MHz
1 34
CKIO clock output cycle time
t_CKOcyc
CKIO clock output low-level pulse width
t_CKOL1
CKIO clock output high-level pulse width
t_CKOH1
CKIO clock output rise time
t_CKOr
CKIO clock output fall time
t
CKOf
CKIO clock output low-level pulse width
t_CKOL2
CKIO clock output high-level pulse width
t_CKOH2
Power-on oscillation settling time
t_OSC1
Power-on oscillation settling time/mode setting t_OSCMD
MD reset setup time
t_MDRS
MD reset hold time
t_MDRH
RESET assert time
t_RESW
15 1000 ns 33.2
1  ns 33.2
1  ns 33.2
 3 ns 33.2
 3 ns 33.2
3  ns 33.3
3  ns 33.3
10  ms 33.6, 33.8
10  ms 33.6, 33.8
3
 t_cyc 33.14
20  ns 33.6, 33.8
20  t_cyc 33.6, 33.7, 33.8, 33.9
Rev. 1.0, 02/03, page 1199 of 1294