SH7760 Datasheet, PDF (654/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 18.2 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
Standby
by RESET Sleep
by
Pin/WDT/
by Sleep
Software/
Multiple
Instruction/ by
Each
Exception Deep Sleep Hardware Module
Serial mode register
SISMR H’20
H’20
Retained
* Retained
Bit rate register
SIBRR H’07
H’07
Retained
Retained
Serial control register
SISCR H’00
H’00
Retained
Retained
Transmit data register
SITDR H’FF
H’FF
Retained
Retained
Serial status register
SISSR H’84
H’84
Retained
Retained
Receive data register
SIRDR H’00
H’00
Retained
Retained
Smart card mode register
SISCMR H’01
H’01
Retained
Retained
Serial control 2 register
SISC2R H’00
H’00
Retained
Retained
Wait time register
SIWAIT H’0000
H’0000
Retained
Retained
Guard extension register
SIGRD H’00
H’00
Retained
Retained
Sampling register
SISMPL H’0173
H’0173
Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the
RESET pin.
Rev. 1.0,02/03, page 604 of 1294