SH7760 Datasheet, PDF (256/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 9.2 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual
Reset by
RESET
Pin/WDT/
Multiple
Exception
Standby
Sleep
by
by Sleep
Software/
Instruction/ by
Each
Deep Sleep Hardware Module
Interrupt control register
H’0000*¹
H’0000*¹ Retained
ICR
H’8000*²
H’8000*² Retained
* Retained
Retained
Interrupt priority level setting register A IPRA
H’0000
H’0000
Retained
Retained
Interrupt priority level setting register B IPRB
H’0000
H’0000
Retained
Retained
Interrupt priority level setting register C IPRC
H’0000
H’0000
Retained
Retained
Interrupt priority level setting register D IPRD
H’DA74
H’DA74
Retained
Retained
Interrupt priority level setting register 00 INTPRI00 H’0000 0000 Retained Retained
Retained
Interrupt priority level setting register 04 INTPRI04 H’0000 0000 Retained Retained
Retained
Interrupt priority level setting register 08 INTPRI08 H’0000 0000 Retained Retained
Retained
Interrupt priority level setting register 0C INTPRI0C H’0000 0000 Retained Retained
Retained
Interrupt source register 00
INTREQ00 H’0000 0000 Retained Retained
Retained
Interrupt source register 04
INTREQ04 H’0000 0000 Retained Retained
Retained
Interrupt mask register 00
INTMSK00 H’F3FF 7FFF Retained Retained
Retained
Interrupt mask register 04
INTMSK04 H’00FF FFFF Retained Retained
Retained
Interrupt mask clear register 00
INTMSK —
—
—
—
CLR00
Interrupt mask clear register 04
INTMSK —
—
—
—
CLR04
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the
RESET pin.
1. The NMI pin is a low level.
2. The NMI pin is a high level.
Rev. 1.0, 02/03, page 206 of 1294