SH7760 Datasheet, PDF (829/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
12
TST4
0
R/W Auto Acknowledge Mode
Allows HCAN2 to generate its own Acknowledge
bit in order to enable Self Test. In order to achieve
the Self Test mode, the message transmitted
needs to be read back, and there are two settings
for this. One is to set [Enable Internal Loop = 1 &
Disable Tx Output = 1 & Disable Rx Input = 1], so
that the Tx value can be internally provided to the
Rx. The other way is to set [Enable Internal Loop
= 0 & Disable Tx Output = 0 & Disable Rx Input =
0] and connect the Tx and Rx onto the CAN bus
so that the transmitted data can be received via
the CAN bus.
0: HCAN2 does not generate its own
Acknowledge bit.
1: HCAN2 generates its own Acknowledge bit.
11
TST3
0
10
TST2
0
R/W Disable Error Counters
Enables/disables the Error Counters (TEC/REC)
to be functional. When this bit is disabled (set to
1), the Error Counters (TEC/REC) remain
unchanged and hold their current value. When
this bit is enabled (cleared to 0), the Error
Counters (TEC/REC) function according to the
CAN specification.
0: Error Counters (TEC/REC) function according
to the CAN specification.
1: Error Counters (TEC/REC) remain unchanged
and holds the current value.
R/W Disable Rx InputControls the Rx to be supplied
into the CAN Interface block. When this bit is
enabled (cleared to 0), the Rx pin value is
supplied into the CAN Interface block. When this
bit is disabled (set to 1), the Rx value for the CAN
block always remains recessive or the Tx value
internally connected if Enable Internal Loop = 1.
0: External Rx pin value is supplied for the CAN
Interface block.
1: Internal Loop Enable = 0: Rx value always
remains recessive for the CAN Interface block.
Internal Loop Enable = 1: Tx value is internally
supplied for the CAN Interface block.
Rev. 1.0, 02/03, page 779 of 1294