SH7760 Datasheet, PDF (689/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 19.2 Register Configuration (1)
Ch. Register Name
Abbrev. R/W P4 Address Area 7 Address Size
0 Slave control register 0
ICSCR0 R/W H’FE14 0000 H’1E14 0000 32
Master control register 0
ICMCR0 R/W H’FE14 0004 H’1E14 0004
32
Slave status register 0
Master status register 0
ICSSR0 R/(W)*¹ H’FE14 0008 H’1E14 0008
32
ICMSR0 R/(W)*² H’FE14 000C H’1E14 000C 32
Slave interrupt enable register 0 ICSIER0 R/W H’FE14 0010 H’1E14 0010 32
Master interrupt enable register 0 ICMIER0 R/W H’FE14 0014 H’1E14 0014
32
Clock control register 0
ICCCR0 R/W H’FE14 0018 H’1E14 0018 32
Slave address enable register 0 ICSAR0 R/W H’FE14 001C H’1E14 001C 32
Master address enable register 0 ICMAR0 R/W H’FE14 0020 H’1E14 0020
32
Receive data register 0
ICRXD0 R/W H’FE14 0024 H’1E14 0024 32
Transmit data register 0
ICTXD0 R/W H’FE14 0024 H’1E14 0024 32
FIFO control register 0
ICFCR0 R/W H’FE14 0028 H’1E14 0028 32
FIFO status register 0
ICFSR0 R/W H’FE14 002C H’1E14 002C 32
FIFO interrupt enable register 0 ICFIER0 R/W H’FE14 0030 H’1E14 0030
32
Receive FIFO data count register 0 ICRFDR0 R
H’FE14 0034 H’1E14 0034 32
Transmit FIFO data count register 0 ICTFDR0 R
H’FE14 0038 H’1E14 0038
32
1 Slave control register 1
ICSCR1 R/W H’FE15 0000 H’1E15 0000 32
Master control register 1
ICMCR1 R/W H’FE15 0004 H’1E15 0004
32
Slave status register 1
Master status register 1
ICSSR1 R/(W)*¹ H’FE15 0008 H’1E15 0008
32
ICMSR1 R/(W)*² H’FE15 000C H’1E15 000C 32
Slave interrupt enable register 1 ICSIER1 R/W H’FE15 0010 H’1E15 0010 32
Master interrupt enable register 1 ICMIER1 R/W H’FE15 0014 H’1E15 0014
32
Clock control register 1
ICCCR1 R/W H’FE15 0018 H’1E15 0018 32
Slave address enable register 1 ICSAR1 R/W H’FE15 001C H’1E15 001C 32
Master address enable register 1 ICMAR1 R/W H’FE15 0020 H’1E15 0020
32
Receive data register 1
ICRXD1 R/W H’FE15 0024 H’1E15 0024 32
Transmit data register 1
ICTXD1 R/W H’FE15 0024 H’1E15 0024 32
FIFO control register 1
ICFCR1 R/W H’FE15 0028 H’1E15 0028 32
FIFO status register 1
ICFSR1 R/W H’FE15 002C H’1E15 002C 32
FIFO interrupt enable register 1 ICFIER1 R/W H’FE15 0030 H’1E15 0030
32
Receive FIFO data count register 1 ICRFDR1 R
H’FE15 0034 H’1E15 0034 32
Transmit FIFO data count register 1 ICTFDR1 R
H’FE15 0038 H’1E15 0038
32
Sync
Clock
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Rev. 1.0, 02/03, page 639 of 1294