SH7760 Datasheet, PDF (1306/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 33.24 AC Characteristics of 80 Series Bus
Item
Symbol
Min.
Max.
Unit Figure
Read bus cycle time
t_MFICYCR
4× t_Pcyc
—
ns 33.73, 33.74
Write bus cycle time
t_MFICYCW
3× t_Pcyc
—
ns
Address setup time
t
0
MFIAS
—
ns
Address hold time
t
0
MFIAH
—
ns
Read low width (Read)
t_MFIWRL
2.5× t_Pcyc
—
ns
Write low width (Write)
t_MFIWWL
1.5× t_Pcyc
—
ns
Read/Write high width
t_MFIWRWH
2.0× t_Pcyc+5
—
ns
Read data delay time
t
—
MFIRDD
2×
t +10
Pcyc
ns
Read data hold time
t
0
MFIRDH
—
ns
Write data setup time
t
t +10
—
ns
MFIWDS
Pcyc
Write data hold time
t_MFIWDH
10
—
ns
Notes: 1. t_Pcyc : one Pck cycle time
2. t_MFIWRL is the time where the low level of MFI-CS and the low level of MFI-RW/RD are
overlapped.
3. t_MFIWWL is the time where the low level of MFI-CS and the low level of MFI-E/WR are
overlapped.
t_MFICYCR
t_MFICYCW
MFI-RS
MFI-CS
t_MFIWRL
t_MFIWWL
t_MFIAS
t_MFIAH
t_MFIAS
t_MFIAH
MFI-RW/RD
MFI-D15-
MFI-D0
t_MFIRDD
t_MFIWRWH
t_MFIRDH
Read data
t_MFIRDD
t_MFIRDH
Read data
Figure 33.73 AC Characteristics of 80 Series Bus (Read)
Rev. 1.0, 02/03, page 1256 of 1294