SH7760 Datasheet, PDF (939/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

25.3.4 PCM Left Channel Register (HACPCML)
HACPCML is a 32-bit read/write data register used for accessing the left channel of the codec in
digital audio recording or stream playback. To transmit the PCM playback left channel data to the
codec, write the data to HACPCML. To receive the PCM record left channel data from the codec,
read HACPCML. The data is left justified to accommodate a codec with ADC/DAC resolution of
20 bits or less.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
- D19 D18 D17 D16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 20 
Initial Value R/W
All 0
R
19 to 0 D19 to D0 All 0
R/W
Description
Reserved
Always 0 for read and write.
Data 19 to 0
Write the PCM playback left channel data to these
bits. The HAC then transmits the data to the
codec on an on-demand basis.
Read these bits to get the PCM record left
channel data from the codec.
In 16-bit packed DMA mode, HACPCML is defined as follows:
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LD15 LD14 LD13 LD12 LD11 LD-10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 889 of 1294