SH7760 Datasheet, PDF (541/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

14.1 Input/Output Pins
Table 14.2 shows the pins used for power-down mode control.
Table 14.2 Pin Configuration
Pin Name
Processing status 1
Processing status 0
Abbreviation
STATUS1
STATUS0
I/O
Output
Hardware standby
CA
request
Input
Function
Indicate the processor's operating status.
STATUS1 STATUS0 Operating Status
High
High
Low
Low
High
Low
High
Low
Reset
Sleep mode
Standby mode
Normal operation
A transition to hardware standby mode is
made by inputting a low-level to the pin.
14.2 Register Descriptions
The following registers are used for power-down mode control. For details on the addresses of
these registers and the state of registers in each operating mode, see section 32, List of Registers.
Table 14.3 Register Configuration (1)
Register Name
Abbrev.
R/W
Standby control register
STBCR
R/W
Standby control register 2 STBCR2
R/W
Clock stop register 00
CLKSTP00
R/W
Clock stop clear register 00 CLKSTPCLR00 W
P4 Address
H’FFC0 0004
H’FFC0 0010
H’FE0A 0000
H’FE0A 0010
Area 7 Address
H’1FC0 0004
H’1FC0 0010
H’1E0A 0000
H’1E0A 0010
Size
8
8
32
32
Sync
Clock
Pck
Pck
Pck
Pck
Rev. 1.0, 02/03, page 491 of 1294