SH7760 Datasheet, PDF (351/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The control signals for connecting synchronous DRAM are RAS, CASS, RD/WR, CS2 or CS3,
DQM0 to DQM3, and CKE. All signals other than CS2 and CS3 are common to all areas, and
signals other than CKE are valid and latched only when CS2 or CS3 is asserted. Synchronous
DRAM can therefore be connected in parallel to multiple areas. CKE is negated (to low level)
when the frequency is changed, when the clock is unstable during stopping of the clock or
restarting of the clock supply, or when self-refreshing is performed. Otherwise, CKE is always
asserted (to high level).
RAS, CASS, RD/WR, and specific address signals specify commands for synchronous DRAM.
The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL),
precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ), read
with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register
setting (MRS).
Bytes are specified by DQM0 to DQM3. A read/write is performed for the byte where the
corresponding DQM signal is low. When the bus width is 32 bits in big-endian mode, DQM3
specifies an access to address 4n and DQM0 specifies an access to address 4n + 3. In little-
endian mode, DQM3 specifies an access to address 4n + 3 and DQM0 specifies an access to
address 4n.
Figure 10.15 shows an example of the connection of 16M × 16-bit synchronous DRAMs.
This LSI
A11–A2
CKIO
CKE
CS3
RAS
RD
RD/WR
D31–D16
DQM3
DQM2
512k × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
D15–D0
DQM1
DQM0
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
Figure 10.15 Connection Example of Synchronous DRAM with 32-Bit Data Width (Area 3)
Rev. 1.0, 02/03, page 301 of 1294