SH7760 Datasheet, PDF (426/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
17
AM
0
R/W Acknowledge Mode
In dual address mode, selects whether DACK is
output in the data read cycle or write cycle.
In single address mode, DACK is always output
regardless of the setting of this bit.
In external request 2-channel mode, this bit is
valid only in CHCR0 and CHCR1.
In DMABRG mode, this bit is valid in CHCR0 to
CHCR7.
0: DACK is output in read cycles
1: DACK is output in write cycles
16
AL
0
R/W Acknowledge Level
Specifies the DACK signal as active-high or
active-low.
In external request 2-channel mode, this bit is
valid only in CHCR0 and CHCR1.
In DMABRG mode, this bit is invalid and the
DACK polarity is specified by bits AL3 to AL0 in
DMARCR.
0: Active-high output
1: Active-low output
15
DM1
0
14
DM0
0
R/W Destination Address Mode 1 and 0
R/W _{These bits specify incrementing/decrementing of}
the DMA transfer destination address. The
specification of these bits is ignored when data is
transferred from external memory to an external
device in single address mode.
00: Destination address fixed
01: Destination address incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +8 in 64-bit transfer, +32 in 32-byte
burst transfer)
10: Destination address decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit
transfer, –8 in 64-bit transfer, –32 in 32-byte
burst transfer)
11: Setting prohibited
Rev. 1.0, 02/03, page 376 of 1294