SH7760 Datasheet, PDF (617/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that set the serial transmission/reception bit rate in accordance with the
baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR.
SCBRR can always be read from and written to by the CPU.
The SCBRR setting is found from the following equation.
Asynchronous mode:
N=
Pck
× 10⁶ - 1
64 × 2^2n-1 × B
Synchronous mode:
N=
Pck
× 10⁶ - 1
8 × 2^2n-1 × B
Where B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pck: Peripheral module operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See table 17.3 for the relation between n and the clock.)
Table 17.3 SCSMR Settings
n
Clock
CKS1
0
Pck
0
1
Pck/4
0
2
Pck/16
1
3
Pck/64
1
SCSMR Setting
CKS0
0
1
0
1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
Pck × 10⁶
- 1 × 100
(N + 1) × B × 64 × 2^2n-1
Rev. 1.0, 02/03, page 567 of 1294