SH7760 Datasheet, PDF (620/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Notes: *1. Reserved bit in channel 0.
*2. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set.
*3. SCIF_CTS is fixed at active-0 regardless of the input value, and SCIF_RTS output is
also fixed at 0.
*4. A reset operation is performed in the event of a power-on reset or manual reset.
17.3.10 Transmit FIFO Data Count Register (SCTFDR)
SCTFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR.
SCTFDR can always be read from the CPU.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- T7 T6 T5 T4 T3 T2 T1 T0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 8 —
Initial Value R/W
All 0
R
7 to 0 T7 to T0 All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits show the number of untransmitted data
bytes in SCFTDR. A value of H'0000 indicates that
there is no transmit data, and a value of H'0080
indicates that SCFTDR is full of transmit data.
17.3.11 Receive FIFO Data Count Register (SCRFDR)
SCRFDR is a 16-bit register that indicates the number of receive data bytes stored in SCFRDR.
SCRFDR can always be read from the CPU.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- R7 R6 R5 R4 R3 R2 R1 R0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
Bit
Bit Name Initial Value R/W
15 to 8 —
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.0, 02/03, page 570 of 1294