SH7760 Datasheet, PDF (412/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 11.1 shows a block diagram of the DMAC.
On-chip
peripheral
module*²
DREQn*³
DACKn*³
DRAKn*³
Count control
Register control
Activation control
DMAC module
DMAC
register
unit*¹
Transfer request
priority control
Transfer request
acceptance control
DMABRG
Bus interface
32-byte data
buffer
External address/on-chip
peripheral module address
Legend:
Bus state
controller
1. This unit has the following 55 registers.
DMAOR
: DMA operation register
SAR 0 to 7
: DMA source address registers 0 to 7
DAR 0 to 7
: DMA destination address registers 0 to 7
DMATCR 0 to 7
: DMA transfer count registers 0 to 7
CHCR 0 to 7
: DMA channel control registers 0 to 7
DMARSRA
: DMA request resource selection register A
DMARSRB
: DMA request resource selection register B
DMAPCR
: DMA pin control register
The following registers are valid only in DMABRG mode.
DMABRGCR
: DMA BRG control register
DMAATXSAR 0 and 1 : DMA audio source address registers 0 and 1
DMAARXDAR 0 and 1 : DMA audio destination address registers 0 and 1
DMAATXTCR 0 and 1 : DMA audio transmit transfer count registers 0 and 1
DMAARXTCR 0 and 1 : DMA audio receive transfer count registers 0 and 1
DMAACR0 and 1
: DMA audio control registers 0 and 1
DMAATXTCNT 0 and 1 : DMA audio transmit transfer counters 0 and 1
DMAARXTCNT 0 and 1 : DMA audio receive transfer counters 0 and 1
DMAUSAR
: DMA USB source address registers 0 to 7
DMAUDAR
: DMA USB destination address register
DMAURWSZ
: DMA USB R/W size register
DMAUCR
: DMA USB control register
DMARCR
: DMA request control register
External bus
2. The following 14 on-chip peripheral modules can
output DMA transfer requests.
SCIF 0 to 2
HSPI
SIM
MMCIF
ADC
: Serial communication interface 0 to 2
: Serial peripheral interface
: Smartcard interface
: Multimedia card interface
: A/D converter
The following modules can output DMA transfer
requests to the DMABRG.
LCDC
: LCD controller
HAC 0 and 1 : Hitachi audio codec interface 0 and 1
SSI 0 and 1 : Serial sound interface 0 and 1
USB
: USB host
3. n = 0 to 3
Figure 11.1 DMAC Block Diagram
Rev. 1.0, 02/03, page 362 of 1294