SH7760 Datasheet, PDF (1113/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

30.4 Operation
30.4.1 Size of LCD Modules Which Can Be Displayed with this LCDC
This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per
pixel). The image data for display is stored in system memory, which is shared with the CPU.
This LCDC should read the data from system memory before display.
This LSI has a maximum 32-byte burst memory read operation and a 2.4-kbyte line buffer, so
display failure is unlikely. However, there may be some display problems with certain
configurations. A recommended size at the frame rate of 60 Hz is 320 × 240 dots in 16 bpp or 640
× 480 dots in 8-bpp.
Figure 30.2 shows the valid display and the retrace period.
Hsync Signal
H total Time
H AddressableVideo
Vsync Time
Back Porch
Top Border
V Addressable
Video
Bottom Border
Front Porch
Active Video =Top/Left Border + Addressable Video + Bottom/Right Border
Total H Blank = Hsync Time + Back Porch + Front Porch
Total V Blank = Vsync Time + Back Porch + Front Porch
HTCN = H Total Time
HDCN = H Addressable Video
HSYNP = H Addressable Video + Right Border + Front Porch
HSYNW = Hsync Time
VTLN = V Total Time
CDLN = V Addressable Video
VSYNP = V Addressable Video + Bottom Border + Front porch
VSYNW = Vsync Time
Figure 30.2 Valid Display and the Retrace Period
Rev. 1.0, 02/03, page 1063 of 1294