SH7760 Datasheet, PDF (23/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

26.3 Register Descriptions ........................................................................................................911
26.3.1 Mode Register (MODER) ....................................................................................914
26.3.2 Command Type Register (CMDTYR).................................................................915
26.3.3 Response Type Register (RSPTYR) ....................................................................916
26.3.4 Transfer Byte Number Count Register (TBCR) ..................................................919
26.3.5 Command Registers 0 to 5 (CMDR0 to CMDR5) ...............................................920
26.3.6 Response Registers 0 to 16 (RSPR0 to RSPR16) ................................................921
26.3.7 Command Start Register (CMDSTRT)................................................................923
26.3.8 Operation Control Register (OPCR) ....................................................................924
26.3.9 Command Timeout Control Register (CTOCR) ..................................................926
26.3.10 Data Timeout Register (DTOUTR) .....................................................................927
26.3.11 Card Status Register (CSTR) ...............................................................................928
26.3.12 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2) ....................................930
26.3.13 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)...................................932
26.3.14 Transfer Clock Control Register (CLKON).........................................................937
26.3.15 Data Register (DR) ..............................................................................................938
26.3.16 FIFO Pointer Clear Register (FIFOCLR).............................................................939
26.3.17 DMA Control Register (DMACR).......................................................................940
26.3.18 Receive Data Timing Select Register (RDTIMSEL) ...........................................941
26.4 Operation...........................................................................................................................941
26.4.1 Operations in MMC Mode...................................................................................941
26.5 MMCIF Interrupt Sources.................................................................................................964
26.6 Operations when Using DMA...........................................................................................965
26.6.1 Operation in Read Sequence ................................................................................965
26.6.2 Operation in Write Sequence ...............................................................................965
26.7 Register Accesses with Little Endian Specification..........................................................968
Section 27 Multifunctional Interface (MFI) ..................................................... 969
27.1 Features .............................................................................................................................969
27.2 Input/Output Pins ..............................................................................................................971
27.3 Register Descriptions ........................................................................................................972
27.3.1 MFI Index Register (MFIIDX) ............................................................................974
27.3.2 MFI General Status Register (MFIGSR) .............................................................975
27.3.3 MFI Status/Control Register (MFISCR) ..............................................................976
27.3.4 MFI Memory Control Register (MFIMCR).........................................................978
27.3.5 MFI Internal Interrupt Control Register (MFIIICR) ............................................980
27.3.6 MFI External Interrupt Control Register (MFIEICR) ..........................................981
27.3.7 MFI Address Register (MFIADR) .......................................................................982
27.3.8 MFI Data Register (MFIDATA)..........................................................................983
27.4 Operation...........................................................................................................................984
27.4.1 Overview..............................................................................................................984
27.4.2 Connections .........................................................................................................985
Rev. 1.0, 02/03, page xxi of xlviii