SH7760 Datasheet, PDF (155/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(3) Virtual Address Space
Setting the AT bit in MMUCR to 1 enables the P0, P3, and U0 areas of the physical address space
in this LSI to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte page
units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be
increased to a maximum of 256. This is called the virtual address space. Mapping from the virtual
address space to the 29-bit external memory space is carried out using the TLB. Only when area 7
in the external memory space is accessed using the virtual address space, addresses H'1C00 0000
to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area
control register area in the physical address space. The virtual address space is shown in figure
6.5.
When the P0, P3, and U0 areas are mapped onto a PCMCIA interface area by means of the TLB in
the cache enabled state, either the WT bit in CCR must be set to 1 or the C bit in PTEL must be
cleared to 0 for that page. In this case, access to the area is performed using the SA and TC bit
values specified in page units for each TLB page.
Note that the CPU cannot access a PCMCIA interface area through access of the P1, P2, or P4
area. Access to a PCMCIA interface area by the DMAC is always performed using the SSAn,
DSAn, STC, and DTC values in CHCRn of the DMAC. For details, see section 11, Direct
Memory Access Controller (DMAC).
Rev. 1.0, 02/03, page 105 of 1294