SH7760 Datasheet, PDF (722/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(Set the force stop bit.)
(5) Wait for the end of transmission:
(a) Wait for a master event (the MST bit in the master status register).
(b) Reset the MST bit after checking MNR (master NACK received).
19.6.2 Master Receiver (Single Buffer Mode)
In order to set up the master interface to receive a data packet on the I²C bus, take the following
steps.
(1) Load the clock control register:
(a) Set SCL clock generation divider (SCGD) to 01h.
(SCL frequency of 400 kHz)
(b) Set clock division factor (CDF) is set to 2h.
(Off-chip clock(sysclockfreq): 33MHz, on-chip clock (clockfreq): 11 MHz)
(2) Load the master control register and address:
(a) Set address of slave being accessed to master address register and the STM1 bit (read
mode: 1).
(b) Set the Master Control Register to 89h.
(MDBS = 1, MIE = 1, and ESG = 1)
(3) Wait for the address to be output:
(a) Wait for master events (interrupts by the MAT bit and MDR bit in the master status
register).
(b) Set the master control register to 88h (the master device keeps the SCL low level until the
MDR bit is cleared in order to suspend the data reception).
If only one data byte is to be transmitted, set the master control register 8Ah. (This enables
the stop generation). This generates a stop on the bus as soon as one byte has been received.
(c) Reset the MAT bit to 0.
(4) Monitor the progress of data byte reception:
(a) Wait for a master event (the MDR bit in the master status register).
(b) Read data from receive data register.
If the byte preceding the last byte transmitted by the slave device is to be received, for the
last one-byte receive interrupt, i.e., MDR interrupt,
(c) Set the master control register to 8Ah.
(Set the force stop control bit).
(d) Reset the MDR bit.
(5) Wait for the end of transmission:
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