SH7760 Datasheet, PDF (353/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(3) Burst Read
The timing chart for a burst read is shown in figure 10.16. The example below assumes that
two 512k × 16-bit × 2-bank synchronous DRAMs are connected, and a 32-bit data width is
used. The burst length is 4. An ACTV command is output in the Tr cycle and then a READ
command is issued in the Tcl cycle. After 4 cycles, a READA command is issued and the read
data is fetched on the rising edge of the off-chip command clock (CKIO) from cycle Td1 to
cycle Td8. The Tpc cycle is used to wait for completion of auto-precharge based on the
READA command inside the synchronous DRAM, and no new access commands can be
issued to the same bank during this waiting period. In this LSI, the number of Tpc cycles is
determined based on the bits TPC2 to TPC0 in MCR that are specified, and no commands are
issued for the synchronous DRAM during this period.
The example in figure 10.16 shows the basic cycle. To connect slower synchronous DRAM,
setting bits WCR2 and MCR can extend the cycle. The bits RCD1 and RCD0 in MCR can be
used to specify the number of cycles from the ACTV command output cycle Tr to the READ
command output cycle Tc1, with the values of 0 to 3 corresponding to 2 to 4 cycles,
respectively. For 2 or more cycles, a Trw cycle, which issues an NOP command for the
synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. Bits A2W2 to A2W0
and A3W2 to A3W0 in WCR2 can be used to specify the number of cycles from READ
command output cycle Tc1 to the first read data latch cycle Td1 as 1 to 5 cycles independently
for areas 2 and 3. This number of cycles corresponds to the number of synchronous DRAM
CAS latency cycles.
Rev. 1.0, 02/03, page 303 of 1294