SH7760 Datasheet, PDF (348/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(4) DCK, BS2, and CS1 Timing when Setting Clock Division Register
Figure 10.13 shows the SRAM read timing when the division ratio is set to CKIO/2 by
DIV[1:0] in DCKDR.
CKIO
A25−A0
CS1
RD/WR
RD
D31−D0
(read)
BS
DCK
BS2
TS1 T1 Tw Tw Tw T2 TH1 TH2
Figure 10.13 DCK, BS2, and CS1 Timing when Reading SRAM Interface
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles)
Rev. 1.0, 02/03, page 298 of 1294