SH7760 Datasheet, PDF (442/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
31
A1RXHE
0
R/W HAC(1)/SSI(1) Receive Side Half Data Transfer
End Interrupt Enable
0: Disabled
1: Enabled
30
A1RXEE
0
R/W HAC(1)/SSI(1) Receive Side All Data Transfer End
Interrupt Enable
0: Disabled
1: Enabled
29
A1TXHE
0
R/W HAC(1)/SSI(1) Transmit Side Half Data Transfer
End Interrupt Enable
0: Disabled
1: Enabled
28
A1TXEE
0
R/W HAC(1)/SSI(1) Transmit Side All Data Transfer
End Interrupt Enable
0: Disabled
1: Enabled
27
A0RXHE
0
R/W HAC(0)/SSI(0) Receive Side Half Data Transfer
End Interrupt Enable
0: Disabled
1: Enabled
26
A0RXEE
0
R/W HAC(0)/SSI(0) Receive Side All Data Transfer End
Interrupt Enable
0: Disabled
1: Enabled
25
A0TXHE
0
R/W HAC(0)/SSI(0) Transmit Side Half Data Transfer
End Interrupt Enable
0: Disabled
1: Enabled
24
A0TXEE
0
R/W HAC(0)/SSI(0) Transmit Side All Data Transfer
End Interrupt Enable
0: Disabled
1: Enabled
Rev. 1.0, 02/03, page 392 of 1294