SH7760 Datasheet, PDF (652/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 18.1 shows a block diagram of the SIM.
SIM internal bus
Peripheral bus
SIM_D
SIM_CLK
SIM_RST
SIRDR
SITDR
SIRSR
Parity check
SITSR
Parity
generation
SISMR
Transmit/ _SISCR
receive
control ^SISSR
SISCMR
SISC2R
SIWAIT
SIGRD
SIBRR
SISMPL
Baud rate
generator
Serial clock
ERI
TXI
RXI
TEI
Receive data full
Transmit data empty
SISCMR: Smart card mode register
SIRSR : Receive shift register
SIRDR : Receive data register
SITSR : Transmit shift register
SITDR : Transmit data register
SISMR : Serial mode register
SISCR : Serial control register
SISC2R : Serial control 2 register
SISSR : Serial status register
SIBRR : Bit rate register
SIWAIT : Wait time register
SIGRD : Guard extension register
SISMPL : Sampling register
Figure 18.1 Block Diagram of SIM
Pck
Interrupt
controller
DMA
controller
18.2 Input/Output Pins
The pin configuration of the SIM is shown in table 18.1.
Table 18.1 Pin Configuration
Name
Transmit/receive data
Clock output
Smart card reset
Abbreviation
SIM_D
SIM_CLK
SIM_RST
I/O
Input/Output
Output
Output
Function
Transmit/receive data input/output
Clock output
Smart card reset output
Rev. 1.0,02/03, page 602 of 1294