SH7760 Datasheet, PDF (195/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

7.2.3 Queue Address Control Register 1 (QACR1)
QACR1 can be accessed in longwords from H'FF00 003C in the P4 area and from H'1F00 003C in
area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is
off.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
AREA1
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R
R
Bit
Bit Name
31 to 5 
4 to 2 AREA1
1, 0

Initial Value R/W Description

R
Reserved
These bits are always read as 0. The write value
should always be 0.

R/W When the MMU is off, these bits generate external
address bits [28:26] for SQ1.

R
Reserved
These bits are always read as 0. The write value
should always be 0.
7.3 Operand Cache Operation
7.3.1 Read Operation
When the OC is enabled (OCE = 1 in CCR) and data is read by means of an effective address from
a cacheable area, the cache operates as follows:
1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
• If the tag matches and the V bit is 1
→ 3.
• If the tag matches and the V bit is 0
→ 4.
• If the tag does not match and the V bit is 0
→ 4.
• If the tag does not match, the V bit is 1, and the U bit is 0 → 4.
• If the tag does not match, the V bit is 1, and the U bit is 1 → 5.
Rev. 1.0, 02/03, page 145 of 1294