SH7760 Datasheet, PDF (432/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.3.5 DMA Operation Register (DMAOR)
DMAOR is a 32-bit readable/writable register that specifies the DMA mode and channel priorities,
and enables or disables DMA transfer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DMS1 DMS0 -
-
-
- PR1 PR0 -
-
-
-
- AE NMIF DME
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R R/W R/W R
R
R
R
R R/W R/W R/W
Bit
Bit Name
31 to 16 —
15
DMS1
14
DMS0
13 to 10 —
9
PR1
8
PR0
Initial Value R/W
All 0
R
0
R/W
0
R/W
All 0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Mode Select 1 and 0
These bits select the transfer mode. Set these bits
when DMAOR.DME = 0.
00: External-request 2-channel mode
11: DMABRG mode*
Other than above: Setting prohibited
Note: * Make this setting when CHCR0 has its
initial value of H’0000 0000.
Reserved
These bits are always read as 0.The write value
should always be 0.
Priority Mode 1 and 0
These bits determine the order of priority for
channel execution when transfer requests are
made for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 >
CH6 > CH7
01: CH0 > CH2 > CH3 > CH4 > CH5 > CH6 >
CH7 > CH1
10: CH2 > CH0 > CH1 > CH3 > CH4 > CH5 >
CH6 > CH7
11: Round robin mode
Rev. 1.0, 02/03, page 382 of 1294