SH7760 Datasheet, PDF (174/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.5 MMU Exceptions
There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss
exception, instruction TLB protection violation exception, data TLB multiple hit exception, data
TLB miss exception, data TLB protection violation exception, and initial page write exception.
Refer to figures 6.9 and 6.10 for the conditions under which each of these exceptions occurs.
6.5.1 Instruction TLB Multiple Hit Exception
An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the
virtual address to which an instruction access has been made. If multiple hits occur when the
UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit
exception will result.
When an instruction TLB multiple hit exception occurs, a reset is executed and cache coherency is
not guaranteed.
Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries
out the following processing:
1. Sets the virtual address at which the exception occurred in TEA.
2. Sets exception code H'140 in EXPEVT.
3. Branches to the reset handling routine (H'A000 0000).
Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception
are checked in the reset handling routine. This exception is intended for use in program
debugging, and should not normally be generated.
Rev. 1.0, 02/03, page 124 of 1294