SH7760 Datasheet, PDF (787/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

21.3.15 Frame Remaining Register (HcFmRemaining)
HcFmRemaining contains a 14-bit down-counter that indicates bit times remaining until the
current frame is complete. HcFmRemaining is a read-only register. Operation is not guaranteed
when writing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRT -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
FR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
31
30 to 14
13 to 0
Bit Name Initial Value R/W Description
FRT
0
R
Frame Remaining Toggle
When FR reaches H′0000, this bit stores the FIT
value in HcFmInterval.
This bit is used by HCD for the synchronization
between the FI and FR bits.

All 0
R
Reserved
These bits are always read as 0.
FR
All 0
R
Frame Bit Times Remaining
This counter is decremented at each bit time. When
it reaches zero, it is re-set to the FI value in
HcFmInterval that is loaded at the next bit time
boundary. When entering the USB operational state,
HC re-loads the contents of the FI bit in
HcFmInterval to this counter and uses the updated
value from the next SOF.
21.3.16 Frame Number Register (HcFmNumber)
HcFmNumber contains a 16-bit counter. This register is referenced for the timing between events
occurring in HC and HCD. HCD uses 16-bit value specified in this register and generates a 32-bit
frame number without requiring frequent access to the register.
HcFmNumber is a read-only register. Operation is not guaranteed when writing.
Rev. 1.0, 02/03, page 737 of 1294