SH7760 Datasheet, PDF (1055/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 28.3 (9) SDBSR Configuration
Bit Abbreviation
I/O*
Bit Abbreviation
I/O*
10 SCIF2_CTS
Control 4 SCIF2_RXD
Control
9
SCIF1_RXD
IN
3 SCIF1_TXD
IN
8
SCIF1_RXD
OUT
2 SCIF1_TXD
OUT
7
SCIF1_RXD
Control 1 SCIF1_TXD
Control
6
SCIF2_RXD
IN
To TDO
5
SCIF2_RXD
OUT
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven
according to the OUT value.
28.3 Register Descriptions
The H-UDI has the following registers. For details of the addresses of SDIR, SDDR (SDDRH and
SDDRL), and SDINT and the status in each operating mode, see section 32, List of Registers.
Table 28.4 Register Configuration (1)
Register Name
Instruction register
Data register H
Data register L
Interrupt source register
Bypass register
Boundary scan register
CPU Side
Abbrev.
Initial Sync
R/W P4 Address Area 7 Address Size Value*¹ Clock
SDIR
R H’FFF0 0000 H’1FF0 0000 16 H’FFFF Pck
SDDR/SDDRH R/W H’FFF0 0008 H’1FF0 0008 32/16 Undefined Pck
SDDRL
R/W H’FFF0 000A H’1FF0 000A 16 Undefined Pck
SDINT
R/W H’FFF0 0014 H’1FF0 0014 16 H’000 Pck
SDBPR
——
—
— Undefined —
SDBSR
——
—
— Undefined —
Rev. 1.0, 02/03, page 1005 of 1294