SH7760 Datasheet, PDF (655/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.3.1 Serial Mode Register (SISMR)
SISMR is an 8-bit readable/writable register that selects settings for the communication format of
the smart card interface.
Bit: 7
6
5
4
3
2
1
0
-
-
PE O/E
-
-
-
-
Initial value: 0
0
1
0
0
R/W: R
R
R R/W R
0
0
0
R
R
R
Bit
Initial
Bit Name Value R/W
7, 6 
All 0 R
5
PE
1
R
4
O/E
0
R/W
3 to 0 
All 0 R
Description
Reserved
These bits are always read as 0, and the write value
should always be 0.
Parity Enable
This bit is always read as 1.The write value should always
be 1.
Parity Mode
Selects whether even or odd parity is to be used when
adding a parity bit and checking parity.
0: Even parity*¹
1: Odd parity*²
Notes: *1. When even parity is specified, the
transmitter will add a parity bit if the
number of transmitted characters (1s) is
odd, so that the total number of set bits
(1s) is always even.
The receiver checks whether the total number
of set bits (1s), including a parity bit and
received characters, is even.
*2. When odd parity is specified, the
transmitter will add a parity bit if the
number of transmitted characters (1s) is
even, so that the total number of set bits
(1s) is always odd.
The receiver checks whether the total number
of set bits (1s), including a parity bit and
received characters, is odd.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.0,02/03, page 605 of 1294