SH7760 Datasheet, PDF (1151/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
13 to 11 —
10
PCBA
9 ,8
—
7
DBEB
6
PCBB
5, 4
—
3
SEQ
Initial Value R/W
All 0
R
—
R/W
All 0
R
—
R/W
—
R/W
All 0
R
—
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Instruction Access Break Select A
Specifies whether a channel A instruction access
cycle break is to be effected before or after the
instruction is executed.
0: Channel A PC break is effected before
instruction execution
1: Channel A PC break is effected after instruction
execution
Reserved
These bits are always read as 0. The write value
should always be 0.
Data Break Enable B
Specifies whether the data bus condition is to be
included in the channel B break conditions. When
the data bus is included in the break conditions,
bits IDB1 to IDB0 in BBRB should be set to B'10 or
B'11.
0: Data bus condition is not included in channel B
break conditions
1: Data bus condition is included in channel B
break conditions
PC Break Select B
Specifies whether a channel B instruction access
cycle break is to be effected before or after the
instruction is executed.
0: Channel B PC break is effected before
instruction execution
1: Channel B PC break is effected after instruction
execution
Reserved
These bits are always read as 0. The write value
should always be 0.
Sequence Condition Select
Specifies whether the conditions for channels A
and B are to be independent or sequential.
0: Channel A and B comparisons are performed as
independent conditions
1: Channel A and B comparisons are performed as
sequential conditions (channel A → channel B)
Rev. 1.0, 02/03, page 1101 of 1294