SH7760 Datasheet, PDF (937/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
31 to 20 
Initial Value R/W
All 0
R
19
RW
0
R/W
18
CA6/SA6 0
R/W
17
CA5/SA5 0
R/W
16
CA4/SA4 0
R/W
15
CA3/SA3 0
R/W
14
CA2/SA2 0
R/W
13
CA1/SA1 0
R/W
12
CA0/SA0 0
R/W
11
SLREQ3 0
R
10
SLREQ4 0
R
9
SLREQ5 0
R
8
SLREQ6 0
R
7
SLREQ7 0
R
6
SLREQ8 0
R
5
SLREQ9 0
R
4
SLREQ10 0
R
3
SLREQ11 0
R
2
SLREQ12 0
R
1, 0

All 0
R
Description
Reserved
Always 0 for read and write.
Codec Read/Write Command
0: Notifies the off-chip codec device of a write
access to the register specified in the address
field (CA6/SA6 to CA0/SA0).
Write the data to HACCSDR in advance.
When HACACR.TX12_ATOMIC is 1, the HAC
transmits HACCSAR and HACCSDR as a pair
in the same Tx frame.
When HACACR.TX12_ATOMIC is 0,
transmission of HACCSAR and HACCSDR in
the same Tx frame is not guaranteed.
1: Notifies the off-chip codec device of a read
access to the register specified in the address
field (CA6/SA6 to CA0/SA0).
Codec Control Register Addresses 6 to 0
/Codec Status Register Addresses 6 to 0
[Write]
Specify the address of the codec register to be
written.
[Read]
Indicate the status address received via slot 1,
corresponding to the codec register whose data
has been returned in HACCSDR.
Slot Requests 3 to 12
Valid only in the Rx frame. Indicate whether the
codec is requesting slot data in the next Tx frame.
Automatically set by hardware, and correspond to
bits 11 to 2 of slot 1 in the Rx frame.
0: Slot data is requested.
1: Slot data is not requested.
Reserved
Always 0 for read and write.
Rev. 1.0, 02/03, page 887 of 1294