SH7760 Datasheet, PDF (1030/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.3.5 MFI Internal Interrupt Control Register (MFIIICR)
The MFIIICR is a 32-bit register that an MFI-connected external device uses to issue interrupts to
the on-chip CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- IIC6 IIC5 IIC4 IIC3 IIC2 IIC1 IIC0 IIR
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Initial
Bit
Name Value R/W Description
31 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
IIC6
0
R/W Internal interrupt source
6
IIC5
0
R/W Bits used to specify the interrupt source generated
5
IIC4
0
R/W by the IIR. Both the MFI-connected external device
4
IIC3
0
R/W and the on-chip CPU can write to these bits. Using
3
IIC2
0
R/W these bits enables fast interrupt handling. These bits
2
IIC1
0
R/W are completely under software control, and their
1
IIC0
0
R/W values have no effect on the operation of the LSI.
0
IIR
0
R/W Internal interrupt request
While this bit is 1, an interrupt request is issued to
the on-chip CPU.
Rev. 1.0, 02/03, page 980 of 1294