SH7760 Datasheet, PDF (727/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

MAT flag
MDE flag
MDT flag
Hardware
S SLAVE ADDRESS A
DATA2
A
DATA2
AP
I²C bus
Write data1
Write data2
Set FSB
[Legend]
(1)
(3)
(5)
(2)
(4)
Clear MAT and MDE
S: Start condition
P: Stop condition
A: Acknowledge
Software
Figure 19.12 Operational Example of Two-byte Data Transmission
(3) Transmission of three or more bytes
Figure 19.13 shows an operational example of three-byte data transmission.
Write data 1 before clearing the MAT and MDE flags in (2) (for example, in initial setting
preceding the issue of start conditions). Once the MDE flag is cleared, data transmission starts.
[Restriction] Write data 2 within eight SCL clock cycles after clearing the MAT and MDE
flags in (2).
Otherwise, data 1 is transmitted twice. If interrupt processing time is too long to write data 2
within eight SCL clock cycles, use FIFO buffer mode.
Write data 3 only after the timing of (8), and hold the MDE flag as 1 until the timing of (8). (If
MDE is set to 1 in (4), refrain from writing data 3 and hold MDE as 1 until (8)). After delaying a
write of data 3, write the succeeding transmit data and set FSB to 1 at the moment of a
transmission stop with MDE =1. Then the fourth and succeeding bytes can be transmitted without
time restriction. To get the timing of (8) ((5) + extra time (1 SCL): it may be longer depending on
the system), use the MDT flag. To get the timing at which the MDT flag is set in (5), clear the
MDT flag to 0 beforehand within eight SCL clock cycles after the MDT flag is first set to 1
(between (6) and (7)). If it is difficult to make the timing of (8), use FIFO buffer mode.
Rev. 1.0, 02/03, page 677 of 1294