SH7760 Datasheet, PDF (1145/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

31.2.3 Break Address Mask Register A (BAMRA)
BAMRA is an 8-bit readable/writable register that specifies which bits are to be masked in the
break ASID set in BASRA and the break address set in BARA.
Bit: 7
6
5
4
3
2
1
0
-
-
-
- BAMA2 BASMA BAMA1 BAMA0
Initial value: ₀
0
0
0
-
-
-
-
R/W: R
R
R
R R/W R/W R/W R/W
Bit
7 to 4
Bit Name
—
2
BASMA
3
BAMA2
1
BAMA1
0
BAMA0
Note: x: Don't care
Initial Value R/W
All 0
R
—
R/W
—
R/W
—
R/W
—
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Break ASID Mask A
Specifies whether all bits of the channel A break
ASID (BASA7 to BASA0) set in BASRA are to be
masked.
0: All BASRA bits are included in break conditions
1: No BASRA bits are included in break conditions
Break Address Mask A2 to A0
These bits specify which bits of the channel A
break address (BAA31 to BAA0) set in BARA are
to be masked.
000: All BARA bits are included in break conditions
001: Lower 10 bits of BARA are masked, and not
included in break conditions
010: Lower 12 bits of BARA are masked, and not
included in break conditions
011: All BARA bits are masked, and not included in
break conditions
100: Lower 16 bits of BARA are masked, and not
included in break conditions
101: Lower 20 bits of BARA are masked, and not
included in break conditions
11x: Setting prohibited
Rev. 1.0, 02/03, page 1095 of 1294