SH7760 Datasheet, PDF (679/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(4) Switching modes
When switching from receiver mode to transmitter mode, after confirming that reception has
been completed, and then set RE = 0 and TE = 1. Completion of reception can be confirmed
through the RDRF flag.
When switching from transmitter mode to receiver mode, after confirming that transmission
has been completed, and then set TE = 0 and RE = 1. Completion of transmission can be
confirmed through the TDRE and TEND flags.
(5) Interrupt operations
The smart card interface has four types of interrupt sources: transmit data empty interrupt
(SIMTXI) requests, transmit/receive error interrupt (SIMERI) requests, receive data full
interrupt (SIMRXI) requests, and transmission end interrupt (SIMTEI) requests.
Table 18.5 describes the interrupt sources for the smart card interface. Each of the interrupt
requests can be enabled or disabled using the TIE, RIE, TEIE, and WAIT_IE bits in SISCR
and the EIO bit in SISC2R. In addition, each interrupt request can be sent independently to the
interrupt controller.
Table 18.5 Smart Card Interface Interrupt Sources
Operating State
Transmitter mode
Receiver mode
Normal operation
Error
Normal operation
Error
Flags
TDRE
TEND
ERS
RDRF
ORER, PER
WAIT_ER
Mask Bits
TIE
TEIE
RIE
RIE, EIO
RIE
WAIT_IE
Interrupt Sources
SIMTXI
SIMTEI
SIMERI
SIMRXI
SIMERI
SIMERI
(6) Data transfer using DMAC
The smart card interface enables reception and transmission in T=0 and T=1 modes using
DMAC.
In transmission, when the TDRE flag in SISSR is set to 1, a transmit data empty DMA transfer
request is issued. If a transmit data empty DMA transfer request is set in advance as a DMAC
startup factor, the DMAC can be started and made to transfer data when a transmit data empty
DMA transfer request occurs.
In T = 0 mode, if an error signal is received during transmission, the disputed data is
automatically repeated. This repetition generates no DMA transfer request, so it is possible to
transmit the number of bytes assigned to the DMAC.
For error handling with an interruput request to the CPU in transmission using the DMAC, set
the TIE bit to 0 to disable an SIMTXI request, and set the RIE bit to 1 to enable an SIMERI
request. Clear the ERS flag by sending an interrupt request to the CPU since it is not
automatically cleared once set when an error signal was received.
Rev. 1.0,02/03, page 629 of 1294