SH7760 Datasheet, PDF (1067/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

29.3.1 A/D Conversion Data Registers A to D (ADDRA to ADDRD)
ADDR are 16-bit read-only registers that store the results of A/D conversion, comprising 4
registers from A to D.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D conversion
data register corresponding to the selected channel. The upper 8 bits of the result are stored in the
upper byte (bits 15 to 8) of the A/D conversion data register. The lower 2 bits are stored in the
lower byte (bits 7 and 6). Bits 5 to 0 of an A/D conversion data register are always read as 0.
Table 29.3 indicates the pairings of analog input channels and data registers ADDRA to ADDRD.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
15 to 6
5 to 0
Bit Name
AD9 to AD0
—
Initial
Value R/W
All 0 R
All 0 R
Description
Bit Data (10 bits)
Reserved
These bits are always read as 0, and the write value
should always be 0.
Table 29.3 Analog Input Channels and Corresponding A/D Conversion Data Registers
Analog Input Channel
AN0
AN1
AN2
AN3
A/D Conversion Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev. 1.0, 02/03, page 1017 of 1294