SH7760 Datasheet, PDF (35/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 17.6 SCIF_RXD Pin........................................................................................................548
Figure 17.7 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, and Two Stop Bits) ...........................................578
Figure 17.8 Sample SCIF Initialization Flowchart .....................................................................581
Figure 17.9 Sample Serial Transmission Flowchart ...................................................................582
Figure 17.10 Sample SCIF Transmission Operation
(Example with 8-Bit Data, Parity, One Stop Bit) ..................................................583
Figure 17.11 Sample Operation Using Modem Control (SCIF_CTS)
(Only in Channels 1 and 2)....................................................................................584
Figure 17.12 Sample Serial Reception Flowchart (1) .................................................................585
Figure 17.12 Sample Serial Reception Flowchart (2) .................................................................586
Figure 17.13 Sample SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit) ..................................................587
Figure 17.14 Sample Operation Using Modem Control
(SCIF_RTS) (Only in Channels 1 and 2)...............................................................588
Figure 17.15 Data Format in Clocked Synchronous Communication ........................................588
Figure 17.16 Sample SCIF Initialization Flowchart ...................................................................590
Figure 17.17 Sample Serial Transmission Flowchart .................................................................591
Figure 17.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode ................592
Figure 17.19 Sample Serial Reception Flowchart (1) .................................................................593
Figure 17.19 Sample Serial Reception Flowchart (2) .................................................................594
Figure 17.20 Sample SCIF Reception Operation in Clocked Synchronous Mode .....................594
Figure 17.21 Sample Simultaneous Serial Transmission and Reception Flowchart...................595
Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode ......................................599
Figure 17.23 Example of Synchronization Clock Transfer by DMAC.......................................600
Section 18 SIM Card Module (SIM)
Figure 18.1 Block Diagram of SIM ............................................................................................602
Figure 18.2 Data Format Used by the Smart Card Interface.......................................................622
Figure 18.3 Examples of Initial Character Waveforms ..............................................................624
Figure 18.4 Example of Initialization Flow ................................................................................626
Figure 18.5 Example of Transmission Processing......................................................................627
Figure 18.6 Example of Reception Processing ...........................................................................628
Figure 18.7 Received Data Sampling Timing in Smart Card Mode ...........................................631
Figure 18.8 Retransmission in the Smart Card Interface Reception Mode.................................632
Figure 18.9 Retransmission Standby Mode (clock stopped)
when the Smart Card Interface is in Transmission Mode........................................632
Figure 18.10 TEIE Set Timing ...................................................................................................633
Figure 18.11 Procedure for Stopping the Clock and Restarting..................................................634
Figure 18.12 Example of Smart Card Interface Pin Connections ...............................................635
Section 19 Hitachi I²C Interface
Figure 19.1 I²C Bus Interface Block Diagram ............................................................................638
Figure 19.2 I²C Bus Timing........................................................................................................663
Rev. 1.0, 02/03, page xxxiii of xlviii