SH7760 Datasheet, PDF (987/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

26.3.14 Transfer Clock Control Register (CLKON)
CLKON controls the transfer clock frequency and clock ON/OFF.
Bits CSEL2 to CSEL0 must be set to 100 for the peripheral clock to be 20-MHz in order to
achieve a 20-Mbps transfer clock in the MMCIF. At this time, bits CSEL2 to CSEL0 should be set
to 000 for the 200-kbps transfer clock in Card Identification Mode in MMC mode.
In a command sequence, do not perform clock ON/OFF or frequency modification.
Bit: 7
6
5
CLKON -
-
Initial value: 0
0
0
R/W: R/W R R
4
3
2
1
0
-
- CSEL2 CSEL1 CSEL0
0
0
00
0
R R R/W R/W R/W
Bit
Initial
Bit Name Value
7
CLKON 0
6 to 3 —
All 0
2
CSEL2 0
1
CSEL1 0
0
CSEL0 0
R/W
R/W
R
R/W
R/W
R/W
Description
Clock On
0: Fixes the transfer clock output from the MCCLK pin to
low level.
1: Outputs the transfer clock from the MCCLK pin.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Frequency Select
000: Uses the 1/100-divided peripheral clock as a transfer
clock.
001: Uses the 1/8-divided peripheral clock as a transfer
clock.
010: Uses the 1/4-divided peripheral clock as a transfer
clock.
011: Uses the 1/2-divided peripheral clock as a transfer
clock.
100: Use the peripheral clock as a transfer clock.
101 to 111: Setting prohibited
Rev. 1.0, 02/03, page 937 of 1294