SH7760 Datasheet, PDF (947/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit
28, 27
Bit Name
Bit Name

Initial Value R/W
Initial Value R/W
All 0
R
26
TX12_ATOMIC 1
R/W
25

0
R
24
RXDMAL_EN 0
R/W
23
TXDMAL_EN 0
R/W
22
RXDMAR_EN 0
R/W
21
TXDMAR_EN 0
R/W
20 to 0 
All 0
R
Description
Description
Reserved
Always 0 for read and write.
TX Slot 1 and 2 Atomic Control
0: Transmits TX data in HACCSAR and that
in HACCSDR separately. (Setting
prohibited)
1: Transmits TX data in HACCSAR and that
in HACCSDR in the same frame if bit 19
in HACCSAR is 0 (write). (HACCSAR
must be written last.)
Reserved
Always 0 for read and write.
RX DMA Left Enable
0: Disables 20-bit RX DMA for HACPCML.
1: Enables 20-bit RX DMA is for HACPCML.
TX DMA Left Enable
0: Disables 20-bit TX DMA for HACPCML.
1: Enables 20-bit TX DMA for HACPCML.
RX DMA Right Enable
0: Disables 20-bit RX DMA for HACPCMR.
1: Enables 20-bit RX DMA for HACPCMR.
TX DMA Right Enable
0: Disables 20-bit TX DMA for HACPCMR.
1: Enables 20-bit TX DMA for HACPCMR.
Reserved
Always 0 for read and write.
Rev. 1.0, 02/03, page 897 of 1294