SH7760 Datasheet, PDF (1068/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

29.3.2 A/D Control/Status Register (ADCSR)
ADCSR is a 16-bit readable/writable register that controls A/D conversion operations and displays
the A/D conversion status.
Bit: 15 14 13 12 11 10 9
ADF ADIE ADST DMASL TRGE1 TRGE0 -
Initial value: 0
0
0
0
0
0
0
R/W: R/(W)* R/W R/W R/W R/W R/W R
8
7
6
5
4
3
- CKSL1 CKSL0 MDS1 MDS0 -
0
0
1
0
0
0
R R/W R/W R/W R/W R
2
1
0
-
CH1 CH0
0
0
0
R R/W R/W
Bit
Bit Name
15 ADF
14 ADIE
Initial
Value
0
0
R/W
R/(W)*
R/W
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Clearing conditions]
• When 0 is written after reading ADF = 1 with ADF = 1
• When ADDR is read with DMASL = 1 (DMA transfer)
Note: If 1 is written, the previous value is retained.
[Setting conditions]
• Single mode: A/D conversion ends
• Multi mode: A/D conversion has cycled through the
selected channels (A/D conversion cycles through the
selected channels)
• Scan mode: A/D conversion has cycled through the
selected channels (A/D conversion is continuously
repeated for the selected channels)
When operation is stopped during conversion in multi
mode or scan mode, the ADF bit is not set.
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at the
end of A/D conversion. Do not change the ADIE bit
setting during A/D conversion.
0: A/D conversion end interrupt (ADI) request is disabled
1: A/D conversion end interrupt (ADI) request is enabled
Rev. 1.0, 02/03, page 1018 of 1294