SH7760 Datasheet, PDF (766/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 21.1 shows a block diagram of the USB host module.
USB interrupt
USB control registers
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus1
Host controller
(HC)
Shared memory (8 kbytes)
UCLK
USB_PENC
USB_OVC
USB_DP
USB_DM
USB bus
transceiver/reciever
Legend:
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
: Host controller interface revision register
: Control register
: Command status register
: Interrupt status register
: Interrupt enable register
: Interrupt disable register
: Host controller communication area pointer register
: Period current ED pointer register
: Control head ED pointer register
: Control current ED pointer register
: Bulk head ED pointer register
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus1
: Bulk current ED pointer register
: Done queue head pointer register
: Frame interval register
: Frame remaining register
: Frame number register
: Periodic start register
: Low speed threshold register
: Root hub descriptor A register
: Root hub descriptor B register
: Root hub status register
: Root hub port status 1 register
Figure 21.1 Block Diagram of USB Host Module
Rev. 1.0, 02/03, page 716 of 1294