SH7760 Datasheet, PDF (355/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

There are 4 burst transfers during a read. In cache-through and other DMA read cycles, the BS
signal is asserted and data is latched only in cycle Td1 of cycles Td1 to Td4.
Such dummy cycles increase the memory access time and tend to reduce program execution
speed and DMA transfer speed. It is important both to avoid access to unnecessary cache-
through areas and to use a data structure that allows data to be placed at a 32-byte boundary for
transfer in 32-byte units when carrying out DMA transfer with synchronous DRAM specified
as the source.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc
Row
Row
H/L
Row
c1
c1
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.17 Basic Timing for Synchronous DRAM Single Read
Rev. 1.0, 02/03, page 305 of 1294