SH7760 Datasheet, PDF (564/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.3.4 Timer Control Registers (TCRn) (n = 0 to 2)
The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock,
specifies the edge when an external clock is selected, and controls interrupt generation when the
flag indicating TCNT underflow is set to 1. TCR2 is also used for input capture control and
control of interrupt generation in the event of input capture.
• TCR0 and TCR1
Bit: 15 14 13 12 11 10
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R
9
8
7
-
UNF -
0
0
0
R R/W R
6
5
4
3
2
1
0
- UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
• TCR2
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ICPF UNF ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 10 —
9
ICPF*¹
8
UNF
Initial Value R/W
All 0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Input Capture Interrupt Flag
Status flag, provided in channel 2 only, which
indicates the occurrence of input capture.
0: Input capture has not occurred
[Clearing condition]
When 0 is written to ICPF
1: Input capture has occurred
[Setting condition]
When input capture occurs*²
Underflow Flag
Status flag that indicates the occurrence of TCNT
underflow.
0: TCNT has not underflowed
[Clearing condition]
When 0 is written to UNF
1: TCNT has underflowed
[Setting condition]
When TCNT underflows*²
Rev. 1.0, 02/03, page 514 of 1294