SH7760 Datasheet, PDF (189/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The operand cache of this LSI uses the 2-way set-associative method, and each way is configured
of 512 cache lines. Figure 7.1 shows the configuration of the operand cache.
The instruction cache uses the 2-way set-associative method, and each way is configured of 256
cache lines. Figure 7.2 shows the configuration of the instruction cache.
Effective address
31
26 25
13 12 10
54 2 0
OIX
ORA
22
RAM area
definition
[13]
Entry
selection
9
Address array
(way 0, way 1)
3
0
Tag
UV
[12:5]
Longword (LW)
selection
Data array (way 0, way 1)
LRU
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
511 19 bits 1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit
Compare Compare
way 0 way 1
Read data
Write data
Hit signal
Figure 7.1 Configuration of Operand Cache
Rev. 1.0, 02/03, page 139 of 1294