SH7760 Datasheet, PDF (169/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.3.3 Address Translation Method
Figure 6.9 shows a flowchart of a memory access using the UTLB.
VA is
in P4 area
On-chip I/O access
Data access to virtual address (VA)
VA is
in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
0
CCR.OCE?
1
0
CCR.CB?
1
No _{MMUCR.AT = 1}
Yes
CCR.WT?
0
No
1
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
No
VPNs match
and V = 1
Yes
No
VPNs match
and ASIDs match and
V=1
Yes
Data TLB miss
exception
Only one
No
entry matches
Yes
00 or
01 W
PR?
10
R/W?
R
Data TLB protection
violation exception
0 (User)
SR.MD?
1 (Privileged)
Data TLB multiple
hit exception
11
R/W? ^W
PR?
01 or 11
00 or 10
W _R/W?
R/W? ^W
R
1
R
D?
0
Initial page write
exception
R
Data TLB protection
violation exception
Cache access
in copy-back mode
C=1
No
and CCR.OCE = 1
Yes
0
WT?
1
Cache access
in write-through mode
Memory access
(Non-cacheable)
Figure 6.9 Flowchart of Memory Access Using UTLB
Rev. 1.0, 02/03, page 119 of 1294