SH7760 Datasheet, PDF (399/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
RD/FRAME
D31-D0
CSn
RD/WR
Tm1
Tmd1w Tmd1w
Tmd1
Tmd2
A
D0
D1
RDY
BS
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.53 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait
Inserted, 32-Bit Bus Width, 64-Bit Data Transfer)
Rev. 1.0, 02/03, page 349 of 1294