SH7760 Datasheet, PDF (27/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

33.3.11 GPIO Signal Timing .......................................................................................... 1247
33.3.12 I²C Electrical Characteristics.............................................................................. 1248
33.3.13 HSPI Module Signal Timing.............................................................................. 1251
33.3.14 USB Electrical Characteristics........................................................................... 1252
33.3.15 MFI Electrical Characteristics............................................................................ 1254
33.3.16 SIM Module Signal Timing ............................................................................... 1258
33.3.17 MMCIF Module Signal Timing ......................................................................... 1258
33.3.18 LCDC Module Signal Timing............................................................................ 1260
33.3.19 HAC Interface Module Signal Timing............................................................... 1261
33.3.20 SSI Interface Module Signal Timing ................................................................. 1262
33.4 A/D Converter Characteristics ........................................................................................ 1264
33.5 AC Characteristic Test Conditions.................................................................................. 1265
33.6 Change in Delay Time Based on Load Capacitance ....................................................... 1266
Appendix ...................................................................................................... 1267
A. Package Dimensions ....................................................................................................... 1267
B. Mode Pin Settings ........................................................................................................... 1268
C. Pin Functions .................................................................................................................. 1270
C.1 Pin States................................................................................................................ 1270
C.2 Handling of Unused Pins ....................................................................................... 1279
D. Synchronous DRAM Address Multiplexing Tables........................................................ 1280
E. Instruction Prefetching and Its Side Effects .................................................................... 1291
F. Power-On and Power-Off Procedures............................................................................. 1292
G. Version registers ............................................................................................................. 1293
Rev. 1.0, 02/03, page xxv of xlviii