SH7760 Datasheet, PDF (415/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Pin Name
Abbreviation I/O
Function
DREQ acceptance DRAK3/ DRAK3
confirmation
Output
Notifies acceptance of DMA transfer
request to external device which has
output DREQ3*³
DMA transfer end DACK3 DACK3
notification
Output
Strobe output to external device which
has output DREQ3, regarding DMA
transfer request*³
Notes: *1. Pin DRAK0 or DRAK1 indicates the start of execution only in external request 2-
channel mode.
*2. Pins DRAK2 and DACK2 are multiplexed.
*3. Pins DRAK3 and DACK3 are multiplexed.
11.3 Register Descriptions
The DMAC has the following registers. For details of register addresses and register states during
each process, see section 32, List of Registers. For details regarding the DMA pin control register
(DMAPCR), see section 24.2.34, DMA Pin Control Register (DMAPCR), in section 24, Pin
Function Controller (PFC). In later descriptions, channel numbers are not explicitly mentioned.
Table 11.2 Register Configuration (1)
Ch. Register Name
Abbrev. R/W P4 Address
0
DMA source address register 0
SAR0
R/W H'FFA0 0000
DMA destination address register 0 DAR0
R/W H'FFA0 0004
DMA transfer count register 0
DMATCR0 R/W H'FFA0 0008
DMA channel control register 0
CHCR0 R/W H'FFA0 000C
1
DMA source address register 1
SAR1
R/W H'FFA0 0010
DMA destination address register 1 DAR1
R/W H'FFA0 0014
DMA transfer count register 1
DMATCR1 R/W H'FFA0 0018
DMA channel control register 1
CHCR1 R/W H'FFA0 001C
2
DMA source address register 2
SAR2
R/W H'FFA0 0020
DMA destination address register 2 DAR2
R/W H'FFA0 0024
DMA transfer count register 2
DMATCR2 R/W H'FFA0 0028
DMA channel control register 2
CHCR2 R/W H'FFA0 002C
Area 7 Address
H'1FA0 0000
H'1FA0 0004
H'1FA0 0008
H'1FA0 000C
H'1FA0 0010
H'1FA0 0014
H'1FA0 0018
H'1FA0 001C
H'1FA0 0020
H'1FA0 0024
H'1FA0 0028
H'1FA0 002C
Size
32
32
32
32
32
32
32
32
32
32
32
32
Sync
Clock
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Rev. 1.0, 02/03, page 365 of 1294