SH7760 Datasheet, PDF (26/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

31.2.5 Break Bus Cycle Register A (BBRA)................................................................ 1097
31.2.6 Break Bus Cycle Register B (BBRB) ................................................................ 1098
31.2.7 Break Data Register B (BDRB) ......................................................................... 1099
31.2.8 Break Data Mask Register B (BDMRB)............................................................ 1099
31.2.9 Break Control Register (BRCR) ........................................................................ 1100
31.3 Operation ........................................................................................................................ 1102
31.3.1 Explanation of Terms Relating to Access.......................................................... 1102
31.3.2 Explanation of Terms Instruction Intervals........................................................ 1103
31.3.3 User Break Operation Sequence ........................................................................ 1103
31.3.4 Instruction Access Cycle Break ......................................................................... 1104
31.3.5 Operand Access Cycle Break............................................................................. 1105
31.3.6 Condition Match Flag Setting ............................................................................ 1106
31.3.7 Program Counter (PC) Value Saved .................................................................. 1106
31.3.8 Contiguous A and B Settings for Sequential Conditions ................................... 1107
31.4 Usage Notes .................................................................................................................... 1108
31.5 User Break Debug Support Function .............................................................................. 1109
31.6 Examples of Use ............................................................................................................. 1111
31.7 User Break Controller Stop Function.............................................................................. 1113
31.7.1 Transition to User Break Controller Stopped State............................................ 1113
31.7.2 Cancelling the User Break Controller Stopped State ......................................... 1113
31.7.3 Examples of Stopping and Restarting the User Break Controller...................... 1114
Section 32 List of Registers............................................................................1115
32.1 Register Addresses
(by functional module, in order of the corresponding section numbers)......................... 1116
32.2 Register Bits.................................................................................................................... 1133
32.3 Register States in Each Operating Mode......................................................................... 1177
Section 33 Electrical Characteristics ..............................................................1195
33.1 Absolute Maximum Ratings ........................................................................................... 1195
33.2 DC Characteristics .......................................................................................................... 1196
33.3 AC Characteristics .......................................................................................................... 1198
33.3.1 Clock and Control Signal Timing ...................................................................... 1199
33.3.2 Control Signal Timing ....................................................................................... 1206
33.3.3 Bus Timing ........................................................................................................ 1208
33.3.4 INTC Module Signal Timing............................................................................. 1241
33.3.5 DMAC Module Signal Timing .......................................................................... 1241
33.3.6 TMU Module Signal Timing ............................................................................. 1242
33.3.7 SCIF Module Signal Timing.............................................................................. 1243
33.3.8 H-UDI Module Signal Timing........................................................................... 1244
33.3.9 CMT Module Signal Timing ............................................................................. 1246
33.3.10 HCAN2 Module Signal Timing......................................................................... 1247
Rev. 1.0, 02/03, page xxiv of xlviii